October 17, 2000

In the chips
Convergence engines pour out of processor forum

The chips were flying in San Jose last week. An almost non-stop torrent of announcements, presentations, and demonstrations at Microprocessor Forum 2000 (MPF 2000) offered tantalizing snapshots of the next-generation microprocessors and architectures for handheld multimedia devices, 3G wireless cell phones, Internet appliances, and high-density packet communication networks.

Semiconductor IP startup Chicory Systems demonstrated products based upon an acceleration architecture for AMD processors, which will enable Internet-connected cell phones and PDAs to offer increased processing power for operation in an enterprise computing environment. Chicory claims that its modular platform,
which integrates multiple accelerators as a standard peripheral attached to an AMD processor, dramatically speeds applications as much as 25 times without requiring any modifications to applications, operating systems, or processor cores.

Chicory's HotShot platform has been designed to accelerate critical software environments such as Java, WAP, i-mode, and XML. In addition, HotShot reportedly boosts the processing of multimedia signals using the MPEG, JPEG, and PNG standards. In addition, Chicory reports that its acceleration platform also decreases battery requirements for host code execution by up to 95 percent.

For more information: www.chicorysystems.com

In a similar vein, PicoTurbo announced the development of a 32-bit RISC processor core for low-power consumer and portable 3G wireless-Internet applications. The pT-120 features an enhanced cache controller with 0 to 64 kbytes of data cache and 0 to 64 kbytes of configurable instruction cache. The core boasts the ability to execute ARM (version 4T) instructions, code compression, DSP extensions, and fast context switching. The core can be ported to new process technologies as well as integrated into any low-power device that needs cache control and requires speeds of up to 400 to 500 MHz. In addition, the core offers a small die size—only 2.1 square millimeters when built using a 0.18-micron process.

For more information: www.picoturbo.com

Rise Technology demonstrated the use of its iDragon mP6 processor core in handheld appliances. According to Rise, the processor can play back an entire VCD (video CD) movie when powered by a single AA battery. The demonstration showed the potential of the processor core for future multimedia-enriched handheld appliances such as 3G phones.

The core is based on a super-scalar, super-pipeline, SIMD (single instruction multiple data) multimedia architecture. The iDragon operates within a wide range of voltages from 1.5 to 1.1 volts. The processor also incorporates power-saving features that bring power consumption to a level that's lower than traditional x86 microprocessors and comparable to RISC microprocessors.

For more information: www.rise.com

Hitachi and STMicroelectronics announced their intention to develop next-generation Super-H processor architectures that will be backward compatible with the SH-5 architecture announced by the two companies in October 1999. Products based on the 64-bit SH-6 and SH-7 architectures will target next-generation digital video cameras, video telephones, Internet appliances, and digital TV sets.

Slated for introduction in the second half of 2002, the SH-6 is expected to operate at up to 1 GHz, deliver more than 2 GIPS of performance, and include micro-architecture enhancements for interactive networking applications. The SH-7, which is expected to contain CPU enhancements for multimedia applications, will be defined once the SH-6 architecture has been fully developed.

STMicroelectronics also announced the addition of three devices to its STPC family of x86 PC-compatible SOC (system on chip) devices for the embedded market. Fabricated in ST's 0.25-micron technology, the STPC Atlas, STPC Consumer-II, and STPC Elite provide the required functionality for building information and Internet appliances, thin-client terminals, and communications systems on a single chip.

At the heart of each of these products is a 64-bit, 133-MHz processor containing a 64-bit SDRAM controller that supports data transfer rates of up to 720 MBytes/sec. All three devices also support up to 128 MBytes of SDRAM as well as UMA (unified memory architecture) in which the same memory array serves as CPU main memory and the graphics frame buffer. In addition, these latest STPC devices feature reduced power consumption over earlier offerings, either 2.5 watts (STPC Consumer-II and STPC Atlas) or 1.5 watts (STPC Elite).

For more information: www.st.com

ARM announced its SIMD and Java-enabling Jazelle extensions for the ARM architecture. Designed to increase the processing capability of ARM-powered, battery-operated devices that require low power consumption, the SIMD extensions have been optimized for video and audio software applications.

ARM claims that its Thumb-instruction-set-compatible SIMD extensions deliver up to 1.6 GOPS at 400 MHz and 3.2 GOPS at 800 MHz with a "near zero" increase in power consumption in typical implementations. In many applications that require considerable signal processing, the SIMD extensions eliminate the need for additional hardware accelerators.

The Jazelle architecture extension enables ARM-based devices to directly execute Java byte-code as well as ARM and Thumb instructions. Executing Java byte-code at up to eight times the speed of other Java implementations, Jazelle-enabled devices can run Java applications on low-power ARM core-based systems.

The ARM Jazelle extension executes the Java byte-code directly in the microprocessor core, removing the need for use of an external accelerator. Jazelle further reduces power requirements by placing less demand on system memory and allowing lower-speed operation for equivalent performance. In addition, the extensions are compatible with industry-standard Java run-time environments as well as any OS that has already been ported to the ARM architecture.

For more information: www.arm.com

Improv Systems unveiled three broadband platforms for use in conjunction with voice-over-packet networks. Improv's platform for home-based access devices supports four voice channels running multiple codecs as well as G.168 echo cancellation with a 16-ms tail length. Designed for use by integrated access devices, the Acappella IAD platform provides 16 channels of G.726 with 32 ms of echo cancellation. The Acappella Gateway platform, which has been optimized for applications requiring maximum channel density, delivers 180 channels of G.726 or 150 channels of G.168 echo cancellation with 32-ms tails.

The three Acappella platforms can be implemented either as stand-alone chips or as cores in SOC devices. In addition, each Acappella platform provides a complete software suite for implementing ITU-T voice codecs (G.711, G.723.1, G.726, G.728, and G.729), G.168 echo cancellation, DTMF, call progress tones, silence suppression, comfort-noise generation, and voice-activity detection.

For more information: www.improvsys.com

SiBytes released a new generation of its Mercurian multiprocessors for networking and communications equipment. The SB-1250 provides on-chip symmetric multiprocessing with two SiByte SB-1 CPUs that are completely symmetric. Each processor works with the same physical address space, and either processor can initiate an I/O operation or service interrupts.

Operating at 1 GHz, each CPU delivers 2200 Dhrystone MIPS at about 2.5 watts, or approximately 880 Dhrystone MIPS/watt. The SB-1250 includes a large memory system that can support a peak memory bandwidth of up to 50 Gbits/sec. A 512-kbyte L2 cache is shared by both processors and all I/O DMA masters. In addition, the Mercurian provides an on-chip internal bus, called the ZBbus, that interconnects the CPU cores, cache memory, and I/O and runs at half the CPU core clock with a data width of 256 bits. The 500-MHz ZBbus also offers a peak bandwidth of up to 128 Gbits/sec.

For more information: www.sibyte.com

—Mark Long, News Correspondent